Computer systems, processes for forming a SRAM cell, processes for turning a SRAM cell off, processes for writing a SRAM cell and processes for reading data from a SRAM cell

ABSTRACT

A two-transistor SRAM cell includes a first FET. The first FET is an ultrathin FET of a first polarity type and includes a control electrode, a first load electrode and a second electrode. The first load electrode is coupled to a first control line. The SRAM cell also includes a second FET. The second FET is an ultrathin FET of a second polarity type and includes a gate, a source and a drain. The second FET source is coupled to the first FET gate. The second FET gate is coupled to the first FET drain and the second FET source is coupled to a first potential. The SRAM cell further includes a first load device that is coupled between a second potential and the first FET gate. The SRAM cell additionally includes a second load device coupled between the second FET gate and a second control line.

TECHNICAL FIELD

[0001] This invention relates generally to a four terminal memory cell,a two-transistor SRAM cell, a SRAM array, a computer system, a processfor forming a SRAM cell, a process for turning a SRAM cell OFF, aprocess for writing a SRAM cell and a process for reading data from aSRAM cell.

BACKGROUND OF THE INVENTION

[0002] The reduction in memory cell and other circuit size required forhigh density static random access memories (SRAMs) and other circuitryis a continuing goal in semiconductor fabrication. SRAMs are used inapplications where high-speed random access memories provide significantperformance advantages over other types of random access memories, suchas dynamic random access memories (DRAMs). However, because SRAMs drawgreater electrical power per stored datum than DRAMs, and also becauseSRAM cells typically consume significantly more silicon real estate thanDRAM cells, marked performance advantages are needed in order to justifythe increased real estate and power budgets necessitated by inclusion ofSRAMs. A typical application for SRAM is in what is known as a “cache”memory.

[0003] One or more cache memories are typically coupled to a centralprocessing unit (CPU) or an arithmetic logic unit (ALU) in a processormodule or chip in order to store recently-executed instructions and/ordata of current interest. Due to the fact that many processing tasksinvolve repetitive calculations and thus require the processor tore-execute recently-executed instructions (on, for example, a sequenceof data points), there is a high probability of locating a neededinstruction in the cache memory and thus of providing that instructionmore rapidly via the cache memory than is possible with other kinds ofmemories and/or memory management schemes. As a result, SRAMs canprovide significant performance advantages, particularly in situationswhere large datasets are frequently manipulated.

[0004] One conventional SRAM architecture uses six transistors and isreferenced as a 6T architecture. Another conventional SRAM architectureincludes four transistors and two load devices, usually either resistorsor PMOS active load devices. Either of these architectures results in amemory cell requiring significantly more area than a DRAM cell, but eachprovides significantly improved access time when compared to DRAMarrays.

[0005] One example of a more compact SRAM cell is described in “A 1.9μm² Loadless CMOS Four-Transistor SRAM Cell In A 0.18-μm LogicTechnology”, by K Noda et al., presented at the 1998 InternationalElectron Devices Meeting, 1998, pp. 643-6. The SRAM cell describedtherein achieves dimensions of 1.04 μm×1.86 μM, or about 60 F², where Fis related to a minimum lithographic feature size, as is described inmore detail hereinbelow with reference to FIG. 2. While the area of thisSRAM cell compares favorably to conventional SRAM cell areas (asdescribed in Table 3 of the reference), the area of this SRAM cell isrepresented in the reference to be still at least three to six timesthat of conventional DRAM cells.

[0006] Accordingly, what is needed includes apparatus and methods forproviding compact SRAM cells and memory cell arrays.

SUMMARY

[0007] In a first aspect, the present invention includes a twotransistor memory cell for an 8F² SRAM array. The two-transistor SRAMcell includes a first FET. The first FET is an ultrathin FET of a firstpolarity type and includes a gate, a source and a drain. The source iscoupled to a first control line. The SRAM cell also includes a secondFET. The second FET is an ultrathin FET of a second polarity type andincludes a gate, a source and a drain. The second FET source is coupledto the first FET gate. The second FET gate is coupled to the first FETdrain and the second FET source is coupled to a first potential. TheSRAM cell further includes a first load device that is coupled between asecond potential and the first FET gate. The SRAM cell additionallyincludes a second load device coupled between the second FET gate and asecond control line.

[0008] In another aspect, the present invention includes a computersystem. The computer system includes a central processing unit, an inputinterface and a memory device coupled to the central processing unit.The memory device is configured to store instructions and data for useby the central processing unit. The memory device includes a SRAM arrayformed from cells each including a first load device and a firstultrathin transistor having a power electrode coupled to the first loaddevice. The cells also each include a second load device and a secondultrathin transistor including a power electrode coupled to the secondload device. The first load device is merged with a control electrode ofthe second ultrathin transistor and vice versa.

[0009] In a further aspect, the present invention includes a process forforming a SRAM cell having an area of 8F², or less, wherein F representsone-half of a minimum lithographic pitch of the SRAM cell. The processincludes providing a semiconductive substrate having a firstconductivity type and forming a diffusion region of a secondconductivity type different than the first conductivity type in thesubstrate. The diffusion region is configured to act as a row addressline. The process also includes forming first and second dielectricpillars on the substrate. The first and second pillars each haverespective plan view areas of about F² and are separated by a distanceof about F. One of the first and second pillars is formed atop thediffusion region and another of the first and second pillars is notformed atop the diffusion region. The process further includes formingfirst and second ultrathin transistors and first and second load devicesin a space between the first and second pillars. The first load deviceis merged with the second ultrathin transistor and the second loaddevice is merged with the first ultrathin transistor.

[0010] In a yet further aspect, the present invention includes a processfor writing a SRAM cell to an ON state. The SRAM cell includes twoswitches. One of the two switches is coupled to a row address line and acolumn address line. The process includes modifying a voltage coupled tothe row address line to cause a voltage applied to a control electrodeof the one switch to exceed a threshold voltage for that switch.

BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Embodiments in accordance with the present invention aredescribed below with reference to the following drawings.

[0012]FIG. 1 is a simplified isometric view, shown in partial cutaway,of an 8F² memory cell for a SRAM, in accordance with an embodiment ofthe present invention.

[0013]FIG. 2 is a simplified plan view of the 8F² SRAM cell of FIG. 1,in accordance with an embodiment of the present invention.

[0014]FIG. 3 is a simplified schematic diagram illustrating some aspectsof the SRAM cell of FIGS. 1 and 2, in accordance with an embodiment ofthe present invention.

[0015]FIG. 4 is a simplified schematic diagram of the SRAM cell of FIGS.1 and 2, in accordance with an embodiment of the present invention.

[0016]FIG. 5 is a simplified graph of voltages within the SRAM cell ofFIGS. 1-4 exemplifying some aspects of operation thereof, in accordancewith an embodiment of the present invention.

[0017]FIG. 6 is a simplified graph of voltages within the SRAM cell ofFIGS. 1-4 exemplifying some aspects of operation thereof, in accordancewith an embodiment of the present invention.

[0018] FIGS. 7-12 are simplified side views, in section, illustratingaspects of a process for fabrication of the SRAM cell of FIGS. 1-4, inaccordance with an embodiment of the present invention.

[0019]FIG. 13 is a simplified block diagram of a computer systemincluding one or more memories using the SRAM cell of FIGS. 1 and 2, inaccordance with an embodiment of the present invention.

DETAILED DESCRIPTION

[0020] This disclosure of embodiments in accordance with the presentinvention is submitted in furtherance of the constitutional purposes ofthe U.S. Patent Laws “to promote the progress of science and usefularts” (Article 1, Section 8).

[0021]FIG. 1 is a simplified isometric view, shown in partial cutaway,of an 8F² memory cell 22 for a SRAM, in accordance with an embodiment ofthe present invention. The SRAM cell 22 is formed on a semiconductivesubstrate 24.

[0022] As used herein, the term “semiconductive substrate” is defined tomean any construction comprising semiconductive material, including, butnot limited to, bulk semiconductive materials such as a semiconductivewafer (either alone or in assemblies comprising other materialsthereon), and semiconductive material layers (either alone or inassemblies comprising other materials). The term “substrate” refers toany supporting structure, including, but not limited to, thesemiconductive substrates described above.

[0023] In one embodiment, the semiconductive substrate 24 includessemiconductive material of a first conductivity type. In one embodiment,the semiconductive substrate 24 includes p-type semiconductive material.In one embodiment, the semiconductive substrate 24 includesmonocrystalline silicon, which may be p-type.

[0024] A diffusion region 26 having a second conductivity type,different than the first conductivity type, is formed in the substrate24 using conventional technology. The diffusion region 26 forms anelongated shape comprising a row address line 28 that is coupled to agroup or row of SRAM cells 22. In one embodiment, the diffusion region26 comprises a heavily doped region which may be n-type material.

[0025] A first pillar 30 is formed from an insulator atop the diffusionregion 26, and a second pillar is formed from an insulator adjacent thefirst pillar 30. In one embodiment, the first and second pillars 30, 32comprise silicon dioxide. In one embodiment, the pillars 30, 32 areformed to have a height above the substrate 24 of about 0.2 μm.

[0026] A semiconductive material 34 is disposed atop the pillar 30. Inone embodiment, the semiconductive material 34 comprises conventionalpolycrystalline silicon.

[0027] In one embodiment, the pillar 30 and the semiconductive layer 34have lateral dimensions on the order of 0.1 μm, however, otherdimensions may be employed. In one embodiment, the semiconductivematerial 34 is heavily doped with the second conductivity type at sometime subsequent to formation of the pillar 30, as is discussed below inmore detail with reference to FIGS. 7-12.

[0028] Additional semiconductive material 36 is disposed at a top edgeof a side of the pillar 30 facing the pillar 32 and is formed to includea portion that is electrically coupled to a portion of thesemiconductive material 34. In one embodiment, the semiconductivematerial 36 is heavily doped with the second conductivity type.

[0029] In one embodiment, additional semiconductive material 38 isdisposed elevationally beneath the semiconductive material 36 and inelectrical contact therewith, along a side of the pillar 30. In oneembodiment, the semiconductive material 38 comprises polycrystallinesilicon that is moderately doped with the second conductivity type.

[0030] Further semiconductive material 40 is disposed elevationallybeside and also elevationally below the semiconductive material 38 andin electrical contact therewith, along the side of the pillar 30. In oneembodiment, the semiconductive material 40 comprises polycrystallinesilicon that is moderately doped with the second conductivity type.

[0031] More semiconductive material 42 is disposed along the side of thepillar 30 between the diffusion region 26 and the semiconductivematerial 40 and is electrically coupled therebetween. In one embodiment,the semiconductive material 42 comprises polycrystalline silicon that isheavily doped with the second conductivity type.

[0032] A dielectric layer 44 is disposed along edges of thesemiconductive materials 38, 40 and 42 that face the second pillar 32.The dielectric layer 44 insulates a lower surface of the semiconductivematerial 38. The dielectric layer 44 also extends across a surface ofthe substrate 24 extending from an outer edge of the semiconductivematerial 42 towards the second pillar 32.

[0033] A column address line 50 is conventionally formed elevationallyabove the semiconductive material 34 and in electrical contacttherewith. The column address line 50 is also electrically coupled toother SRAM cells 22 (not illustrated) along an axis that is not parallelto the word line or row address line 28 and that may be orthogonaltherewith. Electrical selection of one of the column address lines 50and one of the row address lines 28 allows a specific one of the SRAMcells 22 to have data written to or read from the specific one of theSRAM cells 22.

[0034] The second pillar 32 includes a top surface having semiconductivematerial 52 disposed thereon. In one embodiment, the semiconductivematerial 52 comprises polycrystalline silicon that is heavily doped withthe first conductivity type at some time subsequent to formation of thepillar 32. In one embodiment, the first and second pillars 30, 32 andthe semiconductive materials 34, 52 are initially formed in commonprocessing acts and the semiconductive materials 34, 52 are doped duringsubsequent and different processing acts.

[0035] Additional semiconductive material 53 is disposed at a top edgeof a side of the pillar 32 facing the pillar 30 and is formed to includea portion that is electrically coupled to a portion of thesemiconductive material 52. In one embodiment, the semiconductivematerial 53 is heavily doped with the first conductivity type.

[0036] In one embodiment, additional semiconductive material 54 isdisposed elevationally beneath the semiconductive material 53 and inelectrical contact therewith, along the side of the pillar 32 facing thepillar 30. In one embodiment, the semiconductive material 54 comprisespolycrystalline silicon that is moderately doped with the firstconductivity type.

[0037] Further semiconductive material 56 is formed beside and alsoelevationally beneath the semiconductive material 54 and in electricalcontact therewith, along the side of the pillar 30. In one embodiment,the semiconductive material 56 comprises polycrystalline silicon that ismoderately doped with the first conductivity type.

[0038] More semiconductive material 58 is disposed along the side of thepillar 32 between semiconductive material comprising the substrate 24and the semiconductive material 56 and is electrically coupledtherebetween. In one embodiment, the semiconductive material 58comprises polycrystalline silicon that is moderately doped with thefirst conductivity type.

[0039] The dielectric layer 44 electrically isolates the semiconductivematerials 38, 40 and 42 from the semiconductive materials 53, 54, 56 and58.

[0040] An electrical contact 60 couples the semiconductive material 52to a suitable voltage. In one embodiment, the electrical contact 60couples the semiconductive material 52 to a power supply voltage.

[0041]FIG. 2 is a simplified plan view of a circuit layout for the 8F²SRAM cell 22 of FIG. 1, in accordance with an embodiment of the presentinvention. The plan view of FIG. 2 illustrates a representation of anarea 70 of the SRAM cell 22.

[0042] The area 70 for the SRAM cell 22 shown in FIG. 2 is equal toabout 4F×2F, or less, where “F” is defined as equal to one-half ofminimum pitch, with minimum pitch (i.e., “P”) being defined as equal tothe smallest distance of a line width (i.e., “W”) plus width of a spaceimmediately adjacent said line on one side of said line between saidline and a next adjacent line in a repeated pattern within the array(i.e.,

[0043] As shown in FIG. 2, S and W are represented as beingapproximately equal, with the result that the area 70 of the SRAM cell22 may be estimated by substituting suitable fractions or multiples of F(as shown in FIG. 2) for dimensions that technically are actuallyfractions or multiples of S, W or P. Thus, in the preferredimplementation, the consumed area 70 of any given SRAM cell 22 is nogreater than about 8F². As a result, the SRAM cell 22 is compact

[0044]FIG. 3 is a simplified schematic diagram illustrating some aspectsof the SRAM cell 22 of FIGS. 1 and 2, in accordance with an embodimentof the present invention. The simplified schematic diagram of FIG. 3 isintended to convey a limited number of concepts with respect to the SRAMcell 22 and is not intended to be interpreted as a literal or completeschematic diagram.

[0045] The SRAM cell 22 may be viewed as including a first switch 80having a first load electrode coupled to the electrical contact 60 and asecond load electrode. A first resistor 82 includes a first terminalcoupled to the second load electrode and a second terminal 85electrically coupled to the substrate 24, represented as ground in FIG.3. A second switch 90 includes a first load electrode coupled to the rowaddress line 28 and a second load electrode. A second resistor 92includes a first terminal electrically coupled to the second loadelectrode of the second switch 90 and a second terminal electricallycoupled to the column address line 50.

[0046]FIG. 4 is a simplified schematic diagram of the SRAM cell 22 ofFIGS. 1 and 2, in accordance with an embodiment of the presentinvention. The simplified schematic diagram of FIG. 4 is intended toconvey a limited number of concepts with respect to the SRAM cell 22 andis not intended to be interpreted as a literal or complete schematicdiagram. In the embodiment shown in FIG. 4, five voltages, designatedV₁, V₂, V₃, V₄ and V₅, respectively, are identified.

[0047] The first voltage V₁ corresponds to the row address line 28. Thesecond voltage V₂ is represented as being derived from a hypotheticalnode corresponding an electrical junction between the second resistor 92and the second load electrode of the second switch 90. The third voltageV₃ corresponds to the electrical contact 60. The fourth voltage V₄ isrepresented as being derived from a hypothetical node corresponding anelectrical junction between the first resistor 82 and the second loadelectrode of the first switch 80. The fifth voltage V₅ corresponds tothe column address line 50.

[0048] The first switch 80 of FIG. 3 corresponds to a PMOS transistor 80shown in FIG. 4. The PMOS transistor 80 includes a control electrode orgate coupled to the voltage V₂. The second switch 90 of FIG. 3corresponds to a NMOS transistor 90 shown in FIG. 4. The NMOS transistor90 includes a control electrode or gate coupled to the voltage V₄.

[0049] With reference now to FIGS. 1, 3 and 4, the first resistor 82corresponds to the semiconductive material 56 and an adjacent portion ofthe semiconductive material 54. The first transistor 90 includes asource/drain formed by the semiconductive material 53 that correspondsto the first load electrode of FIG. 3 and another source/drainrepresented by the semiconductive material 58.

[0050] A portion of the semiconductive material 54 (FIG. 1) not adjacentto the semiconductive material 56 forms a body of the PMOS FET 80 (FIG.4), an adjacent portion of the dielectric material 44 corresponds togate oxide, and the semiconductive material 38 corresponds to both thesecond resistor 92 and the control electrode or gate for the PMOS FET80.

[0051] A portion of the semiconductive material 40 not adjacent thesemiconductive material 38 forms a body of the NMOS FET 90, an adjacentportion of the dielectric material 44 corresponds to gate oxide, and thesemiconductive material 56 corresponds to both the first resistor 82 andthe control electrode or gate for the NMOS FET 90. The semiconductiveregions 38 and 56 thus each form both a gate electrode for a respectiveone of the switches 80 and 90 and a distributed resistor 92, 82.

[0052] The switches 80 and 90 (FIG. 3) thus may each be formed as anultrathin transistor. As used herein, the “ultrathin transistor” isdefined to mean a transistor formed of a semiconductor material having adimension transverse to the gate that is much smaller than any otherdimension of semiconductor material forming the transistor, and thatfurther has a thickness less than a minimum lithographic feature sizewith which the ultrathin transistor is formed.

[0053] All cells 22 in a particular row (i.e., coupled to a particularrow address line 28) may be reset or turned OFF by increasing the rowaddress line 28 voltage V₁ above a threshold voltage V_(TN) of thesecond switch 90. In one embodiment, the voltage V₁ is raised, forexample, to 0.7 volts. In one embodiment, the threshold voltage V_(TN)is about 0.35 volts. In one embodiment, the second voltage V₂ then risesto within a threshold voltage VTP (associated with the first transistor80) of the voltage V₃, turning the first switch 80 OFF. In oneembodiment, the second voltage V₂ then rises to 0.7 volts, turning thefirst switch 80 OFF.

[0054] In one embodiment, a read operation is accomplished by measuringadditional or increased current through the column address line 50 whena total voltage difference between the row address line 28 and thecolumn address line 50 is increased. In one embodiment, the voltagedifference is increased by lowering the row address line 28 voltage V₁below ground reference potential by an amount less than V_(TN). When thesecond switch 90 is ON, it will conduct more current through the columnaddress line 50. When the second switch 90 is OFF, no additional currentwill flow. This allows the data stored in the SRAM cell 22 to be read.

[0055]FIG. 5 is a simplified graph of voltages within the SRAM cell 22of FIGS. 1-4 exemplifying some aspects of operation thereof, inaccordance with an embodiment of the present invention. The graphs ofFIGS. 5 and 6 were derived using SPICE (simulation program forintegrated circuit engineering) models that are shown below in Table I(FIG. 5) and Table II (FIG. 6). The time and voltage scales of FIGS. 5and 6 are in arbitrary units, as noted. In the simulation from whichFIGS. 5 and 6 were derived, the time increments shown correspond to twomicroseconds per division, however, other time scales, switching speedsetc. are also possible. TABLE I SPICE model for turning ON the SRAM cell22 to write data to the SRAM cell 22. *sram turn off cell to on statevdd 3 0 pulse (0.7 0.7 1μ 1μ 1μ 10μ 13μ) vbl 1 0 pulse (0.0 −0.5 2.0μ 1μ1μ 3μ 13μ) vnpwr 5 0 pulse (0.7 0.7 1μ 1μ 1μ 6μ 13μ) r1 4 0 2000k r2 2 5800k m1 2 4 1   0 ntran   I = 1μ w = 1μ m2 4 2 3   3 ptran   l = 1μ w =1μ op model ptran pmos (level=3 tox=110e−10 vto=−0.35 kp=20e−06) modelntran nmos (level=3 tox=95e−10 vto=0.35 kp=50e−06) tran 0.01μ 10μ probeend

[0056] In one embodiment corresponding to the SPICE model shown in TableI, initially (i.e., at left axis) voltages V₁ and V₄ are zero volts, andinitially voltages V₂ and V₃ are approximately 0.7 volts, however, othervoltages are possible. In this embodiment, voltages V₁ and V₂ areapproximately −0.5 volts between times t₂ and t₃.

[0057] In one embodiment, data may be written to the SRAM cell 22 byfirst turning all of the SRAM cells 22 along one row address line 28 toan OFF state, as described above. The column address line 50 ismaintained at a constant voltage V₅, while the voltage V₁ on the rowaddress line 28 is stepped below the reference ground potential,corresponding to an interval between times t₁ and t₂ in FIG. 5. In orderto turn the NMOS transistor 90 ON, the voltage V₁ on the row addressline 28 needs to be set to a value below the threshold voltage V_(TN)for the NMOS transistor 90. This causes the second switch 90 to turn ON.

[0058] As a result, the node voltage V₂ goes low, turning the firstswitch 80 ON. When both the first and second switches 80 and 90 areturned ON in this manner, the row address line 28 may be returned to thesteady state or ground potential and both the first and second switches80, 90 will remain ON, with V₂ LOW and V₄ HIGH.

[0059]FIG. 6 is a simplified graph of voltages within the SRAM cell 22of FIGS. 1-4 exemplifying some aspects of operation thereof, inaccordance with an embodiment of the present invention.

[0060] To cause a SRAM cell 22 that is on the row address line 28 toremain in an OFF state while at least one other SRAM cell 22 on that rowaddress line 28 is being set to an ON state, the voltage V₅ on thecolumn address line 50 coupled to the SRAM cell 22 that is to remain inthe OFF state is raised as shown at time t₁. This prevents the voltageV₂ from going low enough to turn the first switch 80 ON, with the resultthat the SRAM cell 22 will remain in an OFF state.

[0061] In one embodiment, corresponding to the SPICE model shown belowin Table II, the voltage V₅ is switched from 0.7 to 1.0 volts, however,other voltages are possible. In this model, the voltages V₁ and V₄ areinitially (at left axis) zero volts, with voltage V₁ having a value of−0.5 volts at least between times t₂ and t₃. TABLE II SPICE model forturning OFF the SRAM cell 22 to write data to the SRAM cell 22. *sramleave off cell in off state in same row vdd 3 0 pulse (0.7 0.7 1μ 1μ 1μ10μ 13μ) vbl 1 0 pulse (0.0 −0.5 2.0μ 1μ 1μ 3μ 13μ) vnpwr 5 0 pulse (0.71.0 1μ 1μ 1μ 6μ 13μ) r1 4 0 2000k r2 2 5 800k m1 2 4 1   0 ntran  I = 1μw = 1μ m2 4 2 3   3 ptran  I = 1μ w = 1μ op model ptran pmos (level = 3tox = 110e−10 vto = −0.35 kp = 20e−06) model ntran nmos (level = 3 tox =95e−10 vto = 0.35 kp = 50e−06) tran 0.01μ 10μ probe end

[0062] The results shown in FIGS. 5 and 6 show that selected SRAM cells22 in a given row may be selectively programmed to be either ON or OFF,allowing binary data (i.e., ones and zeros) to be stored in respectiveones of the SRAM cells 22.

[0063] When the SRAM cell 22 is initially OFF and only the columnaddress line 50 voltage V₅ increases, for example, from 0.7 to 1.0volts, that SRAM cell 22 remains OFF (in fact, the cell 22 is driveneven farther to the OFF state, because the PMOS transistor 80 gate isdriven even more positive).

[0064] When the SRAM cell 22 is initially ON and the column address line50 voltage V₅ increases, there is only a small increase in the voltageV₂ since the SRAM cell 22 is ratioed much as a static inverter is. Inother words, the resistance of the NMOS transistor 90 is low, when theNMOS transistor 90 is ON, compared to the resistance of the resistor 92.The PMOS transistor 80 remains ON, V₂ remains LOW and V₄ remains HIGH.Thus, when a SRAM cell 22 is not selected by both the row address line28 and the column address line 50, the states of the SRAM cells 22 arenot disturbed.

[0065] FIGS. 7-12 are simplified side views, in section, illustratingaspects of a process for fabrication of the SRAM cell 22 of FIGS. 1-4,in accordance with an embodiment of the present invention.

[0066]FIG. 7 illustrates the pillars 30 and 32, in accordance with anembodiment of the present invention. The pillar 30 is shown formed atopthe diffusion region 26 that forms the row address line 28 of FIG. 1.Caps 100 and 102 formed of semiconductive material are disposed atop thepillars 30, 32, respectively.

[0067] In one embodiment, the first pillar 30 and the material 34 arefabricated by forming a dielectric layer (not illustrated) and thenforming a lightly doped or not intentionally doped semiconductive layer(not illustrated). Formation of these layers is followed by conventionalmasking and conventional anisotropic etching of the semiconductive layerto provide caps 100, 102. This is followed by conventional anisotropicetching of the dielectric layer to form pillars 30, 32 and stripping ofthe mask to provide the structure shown in FIG. 7. The semiconductormaterial 100 is later doped to provide the doped semiconductor material34 of FIG. 1.

[0068]FIG. 8 illustrates the scenario of FIG. 7 at a later stage inprocessing, in accordance with an embodiment of the present invention.Semiconductive material (not illustrated) has been formed over thefeatures of FIG. 7 and has been stripped from some sides of the pillars30, 32, but not from each side of the pillars 30, 32 that faces theother of the pillars 30, 32.

[0069] In one embodiment, a first conventional anisotropic etch isemployed to remove portions of the deposited semiconductive materialthat are disposed on horizontal surfaces of the structures shown inFIGS. 7 and 8. A subsequent conventional masking and etching operationis then employed to leave the semiconductive material 106, 108 disposedon only one side of each of the pillars 30, 32, where the one sides eachface the other of the pillars 30, 32.

[0070] Thus, semiconductive material 106 is disposed along a face of thepillar 30 that faces the pillar 32, but is not disposed on the substrate24 or on faces of the pillar 30 that do not face the pillar 32.Similarly, semiconductive material 108 is disposed along a face of thepillar 32 that faces the pillar 30, but is not disposed on the substrate24 or on faces of the pillar 30 that do not face the pillar 30. In oneembodiment, the semiconductive material 106, 108 comprisespolycrystalline silicon. In one embodiment, the semiconductive material106, 108 is formed to have a thickness (measured along the horizontal inthe view shown in FIG. 8) of about 20 nm., although thinner or thickersemiconductive materials 106, 108 may be employed.

[0071] Conventional masking and doping may be used dope thesemiconductive material 106 to form the semiconductive material 34.Similarly, conventional masking and doping may be used to dope thesemiconductive material 108 to form the semiconductive material 52.

[0072] In one embodiment, the semiconductive material 106, 108 is thenconventionally heat treated to cause the semiconductive material torecrystallize. In one embodiment, the semiconductive material 106, 108is recrystallized along a vertical axis of the pillars 30, 32,respectively.

[0073]FIG. 9 illustrates the scenario of FIG. 8 at a later stage inprocessing, in accordance with an embodiment of the present invention.The heat treatment associated with recrystallization of thesemiconductive material 106, 108 also causes lower regions 42 and 58,and upper regions 36 and 53, to become doped by outdiffusion.

[0074] In one embodiment, the semiconductive material 42 becomes heavilydoped with dopant of the second conductivity type by outdiffusion fromthe diffusion region 26. In one embodiment, the semiconductive material42 becomes doped heavily n-type. In one embodiment, the semiconductivematerial 36 becomes heavily doped with dopant of the second conductivitytype by outdiffusion from the semiconductive material 34. In oneembodiment, the semiconductive material 36 becomes heavily n-type.

[0075] In one embodiment, the region 58 becomes moderately doped withdopant of the first conductivity type by outdiffusion from the substrate24. In one embodiment, the semiconductive material 58 becomes moderatelyp-type. In one embodiment, the semiconductive material 53 becomesheavily doped with dopant of the first conductivity type by outdiffusionfrom the semiconductive material 52. In one embodiment, thesemiconductive material 53 becomes heavily p-type.

[0076]FIG. 10 illustrates the scenario of FIG. 9 at a later stage inprocessing, in accordance with an embodiment of the present invention. Adielectric layer 120 is formed, for example by conventional CVD. In oneembodiment, chemical-mechanical polishing is used to remove thedielectric layer 120 from the semiconductive materials 34 and 52 and toplanarize portions of the dielectric layer 120 to be level with tops ofthe semiconductive materials 34 and 52. In one embodiment, conventionalmasking and etching are then employed to remove portions of thedielectric layer 120 from areas other than a portion of the substrate 24disposed between the pillars 30, 32.

[0077] A dielectric layer (vertical portion of dielectric layer 120,FIG. 10) is then formed along the semiconductive materials 42, 106 and36. In one embodiment, conventional oxidation is used to form thevertical portion of the dielectric layer 120 of silicon dioxide(corresponding to tox=95e−10 in Tables I and II or a gate dielectricthickness of 95 Angstroms).

[0078] Conventional masking and etching are then employed to removeportions of the dielectric layer 120 from areas other than along thesemiconductive materials 42, 106 and 36.

[0079] Conventional deposition techniques are then employed to depositsemiconductor material 122, followed by conventional chemical-mechanicalpolishing for planarization and etching to recess the semiconductormaterial 122 to provide the structure shown in FIG. 10.

[0080] In one embodiment, the semiconductor material 122 comprisessemiconductor material that is lightly doped with the secondconductivity type. In one embodiment, the semiconductor material 122comprises lightly p-type doped semiconductor material. In oneembodiment, conventional CVD is used to form the semiconductor material122. In one embodiment, the semiconductive material 122 comprisespolycrystalline silicon. In one embodiment, 200 nm of lightly-dopedsemiconductive material 122 is formed.

[0081]FIG. 11 illustrates the scenario of FIG. 10 at a later stage inprocessing, in accordance with an embodiment of the present invention.Portions of the dielectric layer 44 adjacent the semiconductive material54, 53 and atop the semiconductive material 56 are then formed. In oneembodiment, conventional oxidation is employed to form dielectricmaterial 44 comprising silicon dioxide on exposed semiconductorsurfaces, followed by conventional masking and etching to removeunwanted silicon dioxide and to provide the structure illustrated inFIG. 11. The vertical portion of the dielectric layer 44 adjacent thesemiconductive material 54 forming a gate dielectric (corresponding totox=10e−10 in Tables I and II or a gate dielectric thickness of 110Angstroms) can be formed by conventional oxidation.

[0082]FIG. 12 illustrates the scenario of FIG. 11 at a later stage inprocessing, in accordance with an embodiment of the present invention.Conventional deposition techniques are then employed to depositsemiconductor material 38, followed by conventional chemical-mechanicalpolishing for planarization and etching to recess the semiconductormaterial 38 to provide the structure shown in FIG. 12.

[0083] In one embodiment, the semiconductor material 38 compriseslightly doped having the first conductivity type. In one embodiment, thesemiconductor material 38 comprises lightly n-type doped semiconductormaterial. In one embodiment, conventional CVD is used to form thesemiconductor material 38 In one embodiment, the semiconductive material38 comprises polycrystalline silicon. In one embodiment, 200 nm oflightly-doped semiconductive material 38 is formed.

[0084] Conventional techniques are then employed provide protectivedielectric material, such as CVD oxide, to planarize the protectivedielectric material and to form interconnections, wiring and othercircuit elements. As a result, a very efficient SRAM cell 22 is providedhaving a “footprint” of about 8F². This is approximately a factor offive smaller than conventional planar SRAM structures. Data storagedensities of up to about 1 gigabit per square centimeter, or more, maybe realized via the approach of the present invention.

[0085]FIG. 13 is a simplified block diagram of a computer system 250including one or more cache memories 275 using the 8F² SRAM cells 22 ofFIGS. 1 and 2, in accordance with an embodiment of the presentinvention. The computer system 250 includes a processor 252 forperforming various computing functions, such as executing specificsoftware to perform specific calculations or tasks. The processor 252includes a processor bus 254 that normally includes an address bus, acontrol bus and a data bus.

[0086] In addition, the computer system 250 includes one or more tactileinput devices 264, such as a keyboard or a mouse, coupled to theprocessor 252 to allow an operator to interface with the computer system250. Typically, the computer system 250 also includes one or more outputdevices 266 coupled to the processor 252, such output devices typicallybeing a printer or a video terminal. One or more data storage devices268 are also typically coupled to the processor 252 to allow theprocessor 252 to store data or retrieve data from internal or externalstorage media (not shown). Examples of typical storage devices 268include hard and floppy disks, tape cassettes and compact disk read-onlymemories (CD-ROMs).

[0087] The processor 252 is also typically coupled to cache memory 275by the processor bus 254, and to DRAM 278 through a memory controller280. The memory controller 280 normally includes a control and addressbus 282 that is coupled to the DRAM 278. Forming the SRAM 275 using the8F² architecture of the present invention allows the SRAM 275 to becompact, reducing the size and increasing the amount of available highspeed cache memory of the overall system 250.

[0088] In compliance with the statute, the invention has been describedin language more or less specific as to structural and methodicalfeatures. It is to be understood, however, that the invention is notlimited to the specific features shown and described, since the meansherein disclosed comprise preferred forms of putting the invention intoeffect. The invention is, therefore, claimed in any of its forms ormodifications within the proper scope of the appended claimsappropriately interpreted in accordance with the doctrine ofequivalents.

1. A four terminal memory cell comprising: a first switching devicehaving a control terminal and first and second load terminals, a firstof the load terminals being coupled to a row line; a first load elementhaving a first terminal coupled to the second load terminal and having asecond terminal coupled to a column line; a second switching devicehaving a control terminal and first and second load terminals, the firstload terminal of the second switching device being coupled to thecontrol terminal of the first switching device, the second load terminalof the second switching device being coupled to a first power supply andthe control terminal of the second switching device being coupled to thesecond load terminal of the first switching device; and a second loadelement having a first terminal coupled to a second power supply and asecond terminal coupled to the second load terminal of the secondswitching device.
 2. The memory cell of claim 1, wherein the memory cellcomprises an area of 8F², or less, wherein F represents one-half of aminimum lithographic pitch of the memory cell.
 3. The memory cell ofclaim 1, wherein the first switching device comprises a NMOS transistorwith the control terminal corresponding to a gate of the NMOStransistor, the first load electrode corresponding to a source of theNMOS transistor.
 4. The memory cell of claim 1, wherein the secondswitching device comprises a PMOS transistor,
 5. The memory cell ofclaim 1, wherein the first switching device corresponds to an ultrathinMOSFET of a first polarity and wherein the second switching devicecorresponds to an ultrathin MOSFET of a second polarity different thanthe first polarity.
 6. The memory cell of claim 1, wherein the controlelectrode of the first switching device is formed from the second loadelement and the control electrode of the second switching device isformed from the first load element.
 7. The memory cell of claim 1,wherein the first switching device corresponds to an ultrathin MOSFET ofa first polarity and wherein the second switching device corresponds toan ultrathin MOSFET of a second polarity different than the firstpolarity, and wherein the control electrode of the first switchingdevice is formed from the second load element and the control electrodeof the second switching device is formed from the first load element. 8.A two-transistor SRAM cell comprising: a first FET being an ultrathinFET of a first polarity type and including a gate, a source and a drain,the source being coupled to a first control line; a second FET being anultrathin FET of a second polarity type and including a gate, a sourceand a drain, the source of the second FET being coupled to the gate ofthe first FET, the gate of the second FET being coupled to the drain ofthe first FET and the source of the second FET being coupled to a firstpotential; a first load device coupled between a second potential andthe gate of the first FET; and a second load device coupled between thegate of the second FET and a second control line.
 9. The SRAM cell ofclaim 8, wherein: the first FET is a NMOS FET; and the second FET is aPMOS FET.
 10. The SRAM cell of claim 8, wherein: the second load deviceis merged with the gate of the first FET; and the first load device ismerged with the gate of the second FET.
 11. The SRAM cell of claim 8,wherein the SRAM cell comprises an area of 8F², or less, wherein Frepresents one-half of a minimum lithographic pitch of the SRAM cell.12. The SRAM cell of claim 8, further comprising: a semiconductorsubstrate having a first conductivity type; a diffusion region formed inthe substrate and having a second conductivity type different than thefirst conductivity type; a first dielectric pillar formed atop thediffusion region, the first FET and the second load device being formedalong one side of the first dielectric pillar; and a second dielectricpillar formed atop the substrate, the second FET and the first loaddevice being formed along one side of the second dielectric pillar, theone side of each pillar facing the other pillar.
 13. The SRAM cell ofclaim 8, wherein the first and second FETs comprise polycrystallinesilicon.
 14. The SRAM cell of claim 8, wherein the first and second loaddevices comprise polycrystalline material.
 15. A SRAM array forming amemory comprising a first line having a first potential, a second linehaving a second potential, a plurality of row lines, a plurality ofcolumn lines and a plurality of memory cells, each memory cell of theplurality comprising: a first switching device having a control terminaland first and second load terminals, a first of the load terminals beingcoupled to one of the plurality of row lines; a first load elementhaving a first terminal coupled to the second load terminal and having asecond terminal coupled to one of the plurality of column lines; and asecond switching device having a control terminal and first and secondload terminals, the first load terminal of the second switching devicebeing coupled to the control terminal of the first switching device, thesecond load terminal of the second switching device being coupled to thefirst line and the control terminal of the second switching device beingcoupled to the second load terminal of the first switching device; and asecond load element having a first terminal coupled to the second lineand a second terminal coupled to the second load terminal of the secondswitching device.
 16. The SRAM of claim 15, wherein: the first switchingdevice comprises a first ultrathin transistor; and the second switchingdevice comprises a second ultrathin transistor.
 17. The SRAM of claim15, wherein: the first switching device comprises a NMOS transistor; andthe second switching device comprises a PMOS transistor.
 18. The SRAM ofclaim 15, wherein the memory cell comprises an area of 8F², or less,wherein F represents one-half of a minimum lithographic pitch of theSRAM.
 19. The SRAM of claim 15, wherein: the first switching devicecomprises a NMOS transistor wherein a gate of the NMOS transistor ismerged with the second load element; and the second switching devicecomprises a PMOS transistor wherein a gate of the PMOS transistor ismerged with the first load element.
 20. The SRAM of claim 15, whereinthe first and second switching devices an-d the first and second loadelements comprise polycrystalline material.
 21. A SRAM cell having anarea of 8F², or less, wherein F represents one-half of a minimumlithographic pitch of the SRAM cell.
 22. The SRAM cell of claim 21,wherein the SRAM cell forms a portion of a memory comprising a firstline having a first potential, a second line having a second potential,a plurality of row lines, a plurality of column lines and a plurality ofmemory cells, each SRAM cell comprising: a first switching device havinga control terminal and first and second load terminals, a first of theload terminals being coupled to one of the plurality of row lines; afirst load element having a first terminal coupled to the second loadterminal and having a second terminal coupled to one of the plurality ofcolumn lines; and a second switching device having a control terminaland first and second load terminals, the first load terminal of thesecond switching device being coupled to the control terminal of thefirst switching device, the second load terminal of the second switchingdevice being coupled to the first line and the control terminal of thesecond switching device being coupled to the second load terminal of thefirst switching device; and a second load element having a firstterminal coupled to the second line and a second terminal coupled to thesecond load terminal of the second switching device.
 23. The SRAM cellof claim 21, further comprising: a first load device; a first ultrathintransistor having a power electrode coupled to the first load device; asecond load device; and a second ultrathin transistor including a powerelectrode coupled to the second load device, wherein the first loaddevice is merged with a control electrode of the second ultrathintransistor and vice versa.
 24. The SRAM of claim 21, further comprising:a first load device; a NMOS transistor including a power electrodecoupled to the first load device; a second load device; and a PMOStransistor including a power electrode coupled to the second loaddevice, wherein a gate of the NMOS transistor is merged with the secondload device and a gate of the PMOS transistor is merged with the firstload device.
 25. A computer system comprising: a central processingunit; an input interface coupled to the central processing unit; and amemory device coupled to the central processing unit, the memory devicestoring instructions and data for use by the central processing unit,wherein the memory device includes a SRAM array formed from cells eachincluding in combination: a first load device; a first ultrathintransistor having a power electrode coupled to the first load device; asecond load device; and a second ultrathin transistor including a powerelectrode coupled to the second load device, wherein the first loaddevice is merged with a control electrode of the second ultrathintransistor and vice versa.
 26. The computer system of claim 25, whereinthe first ultrathin transistor comprises a vertical NMOS FET and thesecond ultrathin transistor comprises a vertical PMOS FET.
 27. Thecomputer system of claim 25, wherein the first transistor has a loadelectrode coupled to a row address line and the first load device iscoupled to a column address line.
 28. The computer system of claim 25,wherein the first and second transistors comprise polycrystallinesemiconductor material.
 29. The computer system of claim 25, wherein thefirst and second transistors comprise FETs each having a gate electrode,and the first load device is merged with the gate of the secondtransistor and the second load device is merged with the gate of thefirst transistor.
 30. The computer system of claim 25, wherein each cellcomprises an area of 8F², or less, wherein F represents one-half of aminimum lithographic pitch of the SRAM cell.
 31. A process for forming aSRAM cell having an area of 8F², or less, wherein F represents one-halfof a minimum lithographic pitch of the SRAM cell, the processcomprising: providing a semiconductive substrate having a firstconductivity type: forming a diffusion region of a second conductivitytype different than the first conductivity type in the substrate, thediffusion region being configured to act as a row address line; formingfirst and second dielectric pillars on the substrate, the first andsecond pillars having respective plan view areas of about F² and beingseparated by a distance of about F, one of the first and second pillarsbeing formed atop the diffusion region and another of the first andsecond pillars not being formed atop the diffusion region; and formingfirst and second ultrathin transistors and first and second load devicesin a space between the first and second pillars, the first load devicebeing merged with the second ultrathin transistor and the second loaddevice being merged with the first ultrathin transistor.
 32. The processof claim 31, wherein providing a semiconductive substrate comprisesproviding a p-type silicon substrate and wherein forming a diffusionregion comprises forming an elongated n+ diffusion region configured toperform as a row address line.
 33. The process of claim 31, whereinforming first and second dielectric pillars comprises forming first andsecond silicon dioxide pillars having a thickness of about two thousandAngstroms.
 34. The process of claim 31, wherein forming first and secondultrathin transistors and first and second load devices comprises:forming a first polycrystalline semiconductor layer on a side of thefirst pillar that faces the second pillar; forming a secondpolycrystalline semiconductor layer on a side of the second pillar thatfaces the first pillar; forming a dielectric layer on a surface of thesubstrate between the first and second pillars and extending upwards onan exterior surface of the first polycrystalline semiconductor layer;forming semiconducting material atop a portion of the dielectric layerextending between the first and second pillars, the semiconductingmaterial abutting at least a portion of the dielectric layer formed onthe first polycrystalline layer, the semiconducting material abutting aportion of the second polycrystalline layer; removing exposed portionsof the dielectric layer; forming a second dielectric layer atop thesemiconducting material to extend between the first and secondpolycrystalline semiconductor layers and abutting a portion of thesecond polycrystalline layer; and forming second semiconducting materialatop the second dielectric layer and to extend between the dielectriclayer and the second polycrystalline semiconductor layer.
 35. Theprocess of claim 31, wherein forming first and second dielectric pillarsincludes forming semiconductive material atop the first and secondpillars.
 36. The process of claim 31, wherein forming first and secondultrathin transistors comprises forming a PMOS FET and a NMOS FET. 37.The process of claim 31, wherein forming first and second dielectricpillars comprises anisotropic etching.
 38. A process for turning a SRAMcell OFF comprising increasing a voltage applied to a switch in the SRAMcell above a threshold voltage for that switch.
 39. The process of claim38, wherein the act of turning a SRAM cell OFF comprises turning a rowof SRAM cells OFF.
 40. The process of claim 38, wherein the SRAM cellcomprises a first transistor and a second transistor, wherein the switchcomprises the second transistor and wherein the second transistorcomprises an ultrathin NMOS transistor having a gate, a source, a drainand a threshold voltage, the source being coupled to a row address lineand the drain being coupled to a column address line and wherein the actof turning a SRAM cell OFF comprises raising a voltage coupled to therow address line above the threshold and turning a row of SRAM cellscoupled to that row address line OFF.
 41. The process of claim 38,wherein the act of turning a SRAM cell OFF comprises turning OFF all ofthe transistors in that cell.
 42. The process of claim 38, wherein thefirst transistor comprises an ultrathin PMOS transistor having a gate, asource and a drain and the switch comprises the second transistor, thesecond transistor comprising an ultrathin NMOS transistor having a gate,a source and a drain, the NMOS transistor source being coupled to a rowaddress line and the NMOS transistor drain being coupled to a columnaddress line and wherein the act of turning a SRAM cell OFF comprises:raising a voltage coupled to the row address line above the thresholdand turning the NMOS transistor coupled to that row address line OFF;and causing a source-drain voltage of the PMOS transistor to become lessthan a threshold voltage for the PMOS transistor in response to the NMOStransistor turning OFF.
 43. The process of claim 38, wherein the SRAMcell is coupled to a row address line and wherein the act of turning aSRAM cell OFF comprises raising a voltage coupled to the row addressline from about zero volts to about 0.7 volts or less.
 44. The processof claim 38, wherein the act of turning a SRAM cell OFF comprisesturning OFF both of the two transistors in that cell.
 45. A process forwriting a SRAM cell comprising two switches, where one of the twoswitches is coupled to a row address line and a column address line, toan ON state, comprising modifying a voltage coupled to the row addressline to cause a voltage applied to a control electrode of the one switchto exceed a threshold voltage for that switch.
 46. The process of claim45, further comprising modifying voltages coupled to column addresslines of SRAM cells that are not to be written to the ON state toprevent the row address line voltage modification from turning ONswitches in the SRAM cells that are not to be written to the ON state.47. The process of claim 46, wherein modifying voltages coupled tocolumn address lines comprises raising the voltages coupled to theaddress lines of SRAM cells that are not to be written to the ON state.48. The process of claim 45, wherein at least one of the two switchescomprises a NMOS FET having a gate, drain, source and threshold voltageV_(TN), wherein the source is coupled to the row address line and thedrain is coupled to the column address line, wherein modifying a voltagecoupled to the row address line comprises reducing the voltage coupledto the row address line below ground to cause a voltage applied to thegate to exceed the threshold voltage V_(TN).
 49. The process of claim45, further comprising, prior to modifying a voltage, writing a row ofSRAM cells coupled to the row address line to the OFF state.
 50. Aprocess for reading data from a SRAM cell including a first transistorof a first conductivity type and a second transistor of a secondconductivity type comprising: increasing a voltage across a portion ofthe cell including two power electrodes of one of the first and secondtransistors; and monitoring a current through the power electrodes ofthe one transistor.
 51. The process of claim 50, wherein increasingcomprises increasing the voltage by less than an amount represented by aturn-on voltage of the one transistor.
 52. The process of claim 50,wherein the first transistor comprises an ultrathin PMOS transistor andthe second transistor comprises an ultrathin NMOS transistor, andwherein: increasing comprises lowering a voltage impressed on a sourceof the NMOS transistor below a ground reference voltage; and monitoringcomprises monitoring a drain current of the NMOS transistor.
 53. Theprocess of claim 50, further comprising: determining that a firstlogical state was stored in the SRAM cell when no current increaseaccompanies increasing; and determining that a second logical statedifferent than the first logical state was stored in the SRAM cell whena current increase accompanies increasing.
 54. The process of claim 50,wherein the first transistor comprises an ultrathin PMOS transistorhaving a gate, a source and a drain and the second transistor comprisesan ultrathin NMOS transistor having a gate, a source and a drain, theNMOS transistor source being coupled to a row address line and the NMOStransistor drain being coupled to a column address line and wherein:increasing comprises reducing a potential applied to the row addressline; and monitoring comprises monitoring a current through the columnaddress line.
 55. The process of claim 50, wherein the first transistorcomprises an ultrathin PMOS transistor having a gate, a source and adrain and the second transistor comprises an ultrathin NMOS transistorhaving a gate, a source and a drain and wherein increasing comprisesincreasing a gate-source voltage of the NMOS transistor to a value thatis less than a threshold voltage of the NMOS transistor.